XGSPON Project

XGSPON Project

Project Name: Diseño y desarrollo de una solución backhaul 5G basada en tecnología XGSPON

Leader of the Consortium: TELNET REDES INTELIGENTES, S.A.


Total budget: 742.075 €

UVa budget: 270.675 €

Duration: 36 meses

Start-end date: 01/01/2020 – 31/12/2022

The industrial company TELNET Redes Inteligentes, S.A. hose activity is focused on the telecommunications sector developing solutions for passive base station antennas for 2G/3G/4G networks, optical fibre cables, passive optical components, active fibre optic data transport solutions, fibre optic access solutions based on the GPON standard, as well as gateways and Internet of Things devices (Internet of Things, IoT) and, the University of Valladolid, Public Research Organisation, whose main purpose is within the framework of the promotion of technological activities, combine expertise in multidisciplinary fields to offer technological solutions in the framework of the information and communications society, through their Optical Communications Group (GCO), present the I+D+i project entitled “Design and development of a 5G backhaul solution based on XGSPON technology”.

This project is under the State Programme for Research, Development and Innovation Oriented to the Challenges of Society, within the framework of the State Plan for Scientific and Technical Research and Innovation 2017-2020, which has as its general objective the design and development of a complete fibre optic access equipment architecture which, operating under the XGSPON standard, allows its use not only for broadband access for residential users, but also as backhaul of the 5G SA (Stand Alone) networks that will begin to deploy from 2021/2022. The objective of this project is the HW design and SW programming of the XGSPON header controllers, also called OLTs (Optical Line Terminal), as well as the HW and SW of the XGSPON access equipment, called ONTs (Optical Network Terminator), including a system of global management of the architecture that will allow the operators of the architecture to register in a simple way all the nodes of the network.